The present invention relates to a semiconductor device in which a plurality of FETs (Field Effect Transistors) having different threshold values are formed on the same substrate, and a method of fabricating the semiconductor device.
In recent years, as an integrated circuit to be operated at a high speed and at a high frequency, there has been used a type in which a plurality of FETs having different threshold values, for example, a DFET (Depletion type FET) and an EFET (Enhancement type FET) are formed on the same semiconductor substrate.
The semiconductor device of this type has been known, for example, from Japanese Patent Laid-open No. Hei 2-192734. In this document, there is disclosed a fabrication structure of an invertor circuit composed of a DCFL (Direct Coupled FET Logic) circuit using a MESFET (Schottky Gate Type FET). To be more specific, active layers of a first conducting type (N-type active layers) of a DFET and an EFET are formed at the same ion implantation step, and with respect to the EFET, a layer doped with an impurity of a second conducting type (P-type doped layer) is formed at the bottom portion of the active layer of the first conducting type.
With this configuration, it becomes possible to reduce the number of fabrication steps and hence to increase the yield, to stabilize a balance in threshold value between the DFET and EFET, and to suppress a short channel effect of the EFET.
Incidentally, a semiconductor device having a plurality of FETs having different threshold values is required to be applied to a MMIC (Monolithic Microwave Integrated Circuit) containing a logic circuit, and the like. Such a MMIC has been used for a high frequency circuit block at a terminal of mobile communication such as a PHS. An analog circuit portion of a MMIC includes an antenna switch, a low noise amplifier, a mixer, a power amplifier, and a circuit with these components combined on the same substrate. In such a MMIC, it is required to increase performances of both a DFET and an EFET. To be more specific, in order to improve characteristics, for example, increase a gain or decrease an on-resistance not only in an EFET but also in a DFET, it is required to shorten a gate length or make thin a channel layer and increase an impurity concentration of the channel layer.
In the above-described related art semiconductor device, however, the DFET is used only as a resistance in the DCFL circuit and a buried layer of the second conducting type is not formed at the bottom portion of the DFET, and consequently, there occurs a large short channel effect even in the case where a gate length of the DFET is shortened, and thereby sufficient characteristics of the DFET cannot be obtained and also a controllability of a threshold value of the DFET is degraded. As a result, it fails to attain a high performance of the DFET, thus leading to a problem that the semiconductor device including such a DFET cannot be applied to a MMIC and the like.
On the other hand, in the actual fabrication step, a controllability of a threshold value is degraded due to the fact that a dose of an impurity doped by an ion implantation system varies between batches. To be more specific, in the case where ions of an impurity are implanted in FETs being different in desired threshold value at different steps, there arises a problem that a variation in the dose of the impurity between batches causes a deviation from a desired difference between threshold values of the FETs (hereinafter, referred to as "a relative deviation"), leading to such a failure that if one threshold value is in a suitable range, another one is out of a suitable range.